While some view flash as a competing “main memory” technology [48], these attempts have not yet been successful
PCRAM promises substantial density benefits (at least 2-4X over DRAM today), and it has been studied extensively to replace or augment DRAM in building a higher capacity and more scalable main memory system [5], [30], [49], [52], [66], [64]. However, it is both much slower (about 2-4X read, 10-100X write) and much more power hungry (about 2-4X read, 10-50X write), compared to DRAM [30], [50], [55], [61]. In addition, a PCRAM cell wears out with each write, which leads to a limited lifetime.
Spin-Transfer Torque RAM (STT-RAM) is another competing technology that has also come under much scrutiny recently [8], [15], [23], [54]. STT-RAM does not necessarily have a density benefit over DRAM. While its read performance latency and energy is comparable to that of DRAM, its write performance (latency and energy) is worse (1.25-2X in latency, 5-10X in energy [9], [33]) than that of DRAM.
However, STTRAM has two major advantages over DRAM: non-volatility and decoupled sensing and buffering. When compared to PCRAM, STT-RAM has much better read/write performance and energy characteristics as well as much better write endurance. Yet,
STT-RAM technology has so far only been explored as an SRAM substitute for on-chip caches [27], [53], [56], [57], [62], but has not been considered as a candidate for main memory.
In this paper, we ask (and give a positive architectural answer to) the question: Can STT-RAM be used to completely
replace DRAM main memory? We set out to make STTRAM main memory performance comparable to DRAM main memory while providing substantial power savings.
## 2017 Thesis [Design and development of low-power and reliable logic circuits based on spin-transfer torque magnetic tunnel junctions](https://tel.archives-ouvertes.fr/tel-01643939/document) Erya Deng
## emerging memory technologies
## [Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative](https://users.ece.cmu.edu/~omutlu/pub/sttram_ispass13.pdf) Emre Kultursay
> While some view **flash as a competing “main memory” technology [48]**, these attempts have not yet been successful
> **PCRAM promises substantial density benefits (at least 2-4X over DRAM today)**, and it has been studied extensively to replace or augment DRAM in building a higher capacity and more scalable main memory system [5], [30], [49], [52], [66], [64].
> **However, it is both much slower (about 2-4X read, 10-100X write) and much more power hungry (about 2-4X read, 10-50X write)**, compared to DRAM [30], [50], [55], [61]. In addition, a **PCRAM cell wears out with each write**, which leads to a limited lifetime.
> Spin-Transfer Torque RAM (STT-RAM) is another competing technology that has also come under much scrutiny recently [8], [15], [23], [54]. **STT-RAM does not necessarily have a density benefit over DRAM**. While **its read performance latency and energy** is comparable to that of DRAM, its **write performance (latency and energy) is worse (1.25-2X in latency, 5-10X in energy [9], [33]) than that of DRAM**.
> However, **STTRAM has two major advantages over DRAM: non-volatility and decoupled sensing and buffering**. When compared to PCRAM, STT-RAM has much better read/write performance and energy characteristics as well as much better write endurance. Yet,
> STT-RAM technology has so far only been explored as an SRAM substitute for on-chip caches [27], [53], [56], [57], [62], but has not been considered as a candidate for main memory.
> In this paper, we ask (and give a positive architectural answer to) the question: Can STT-RAM be used to completely
> replace DRAM main memory? **We set out to make STTRAM main memory performance comparable to DRAM main memory while providing substantial power savings**.
## 2014... why things take so long?? Tom Coughlin [Thanks for the Memories](https://www.snia.org/sites/default/files/Coughlin-Grochowski-Thanks_for_the_Memories.pdf)
- [Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5153/suockchung2010.pdf) Suock Chung
**most relevant now** is [Performance, Power, and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-Level Requirement](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5154/li2011.pdf) Hai Li
[C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5155/2541228.2555308.pdf) YONG LI
## basic physics 2020 Nature [Temporal and spectral fingerprints of ultrafast all-coherent spin switching](https://arxiv.org/abs/2001.06255) S. Schlauderer