In this paper, we proposed AILC, a compute-in-memory (CIM)-based accelerator for on-chip incremental learning using STT-MRAM technology.
System-level benchmark shows that AILC could achieve 147×, 3.7×~28.7×, 2.05×~2.9× higher energy efficiency than Nvidia Titan-V GPU, RRAM-based CIM accelerators and edge TPU/GPU, respectively. Compared to the baseline, the throughput of AILC is improved by 2.0×~2.2× on average with the hardware resources assignment protocol, which results in 4.1×~21.4× higher throughput than edge TPU/GPU.
Compared to an SRAMbased implementation, the STT-AI accelerator achieves 75% area and 3% power savings at iso-accuracy. Furthermore, with a relaxed bit error rate and negligible AI accuracy trade-off, the
designed STT-AI Ultra accelerator achieves 75.4%, and 3.5% savings in area and power, respectively over regular SRAM-based accelerators.
## 2021 [AILC: Accelerate On-chip Incremental Learning with Compute-in-Memory Technology](https://ieeexplore.ieee.org/abstract/document/9329153) Yandong Luo; Shimeng Yu
pdf?
> In this paper, we proposed AILC, a compute-in-memory (CIM)-based accelerator for **on-chip incremental learning using STT-MRAM technology.**
> System-level benchmark shows that AILC could achieve 147×, 3.7×~28.7×, 2.05×~2.9× higher energy efficiency than Nvidia Titan-V GPU, RRAM-based CIM accelerators and edge TPU/GPU, respectively. Compared to the baseline, the throughput of AILC is improved by 2.0×~2.2× on average with the hardware resources assignment protocol, which results in 4.1×~21.4× higher throughput than edge TPU/GPU.
## [Yandong Luo](https://scholar.google.com/citations?hl=zh-CN&user=4PQBGVAAAAAJ&view_op=list_works&sortby=pubdate)
2020 [Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training](https://dl.acm.org/doi/10.1109/ASP-DAC47756.2020.9045288)
2020 [Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses](https://dl.acm.org/doi/10.1109/TC.2020.3000218)
2020 [A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out](https://ieeexplore.ieee.org/abstract/document/9181022) Yandong Luo
- [MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations](https://dl.acm.org/doi/pdf/10.1145/3354265.3354266)
2019 [DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies](https://par.nsf.gov/servlets/purl/10181611) Xiaochen Peng
## https://github.com/xialeiliu/Awesome-Incremental-Learning
## 2016 [Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read](https://ieeexplore.ieee.org/abstract/document/7427985)
- Lide Duan
## 2021 [Designing Efficient and High-performance AI Accelerators with Customized STT-MRAM](https://arxiv.org/abs/2104.02199) Kaniz Mishty
> Compared to an SRAMbased implementation, the STT-AI accelerator achieves 75% area and 3% power savings at iso-accuracy. Furthermore, **with a relaxed bit error rate and negligible AI accuracy trade-off**, the
> designed STT-AI Ultra accelerator achieves 75.4%, and 3.5% savings in area and power, respectively over regular SRAM-based accelerators.