## 2019 [MRAM Technology and Business ](https://s3.i-micronews.com/uploads/2019/07/YD19035_MRAM-Technology-and-Business-2019_August_2019_Sample.pdf) 2019

2019 [**MRAM promises life beyond eFlash**: the embedded MRAM market is taking off and is expected to reach $\$ 1.2B$ by 2024.](https://s3.i-micronews.com/uploads/2019/07/YD19035_MRAM-Technology-and-Business-2019_August_2019_Flyer.pdf)

2019 [MRAM: a promising new life after eFlash – An interview with GlobalFoundries](https://www.i-micronews.com/mram-a-promising-new-life-after-eflash/?cn-reloaded=1)

> There is consensus in the industry that **28/22nm will be the end of eFlash**, not because of scalability limitations but because of economic barriers, and therefore a new embedded NVM for code/data storage is needed

https://www.anandtech.com/show/14056/samsung-ships-first-commercial-emram-product

> MRAM is one of the highest-performing and most durable non-volatile memory technologies currently exists. Because its **eMRAM does not require an erase cycle before writing data,** it is **1,000 times faster than eFlash, Samsung says**. It also uses lower voltages when compared to eFlash, and therefore consumes **around 1/400th the energy during writing process, according to the maker.**

## 2019 [Time-to-Market by MRAM industry Players](https://cellar-c2.services.clever-cloud.com/s3.i-micronews.com/uploads/2019/07/Time-to-Market-for-STT-MRAM-players-By-applications-for-leading-players-fabless-stand-alone-and-foundries-embedded.jpg)

## 2016 [Avalanche, Everspin, Global Foundries](https://www.snia.org/sites/default/files/NVM/2016/presentations/Panel_1_Combined_NVM_Futures%20Revision.pdf)

- 2021 Avalanche - the spec [8Mbit – 64Mbit Embedded MRAM Macro (eMRAM)](https://www.avalanche-technology.com/wp-content/uploads/2019/06/8Mb-64Mb-eMRAM.pdf)

## patents

IBM [Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)](https://patents.google.com/patent/US9431084B2/en)

## the WRITE challenges

[Opportunistic Write for Fast and Reliable STT-MRAM](https://dl.acm.org/doi/pdf/10.5555/3130379.3130505)

## the ON/OFF ratio challenge... for the size of MRAM

## circuitry

old 2011 [Cross-point architecture for spin transfer torque magnetic random access memory](https://arxiv.org/ftp/arxiv/papers/1202/1202.1782.pdf)

## 2021 [Only one issue remains unsolved to date: IBM must figure out how to reduce the current needed to switch states by about 50%.](https://www.forbes.com/sites/karlfreund/2021/03/10/ibm-nears-breakthrough-in-new--memory-class/?sh=6cdfc9dff6d5)

1.  The time it takes to switch states must be fast, in the 2-3 nanosecond range.
1.  The switching must be reliable, down to 1e-9 write error rate.
1.  The switching voltage distribution must be in a tight range for consistent operation.
1.  The fabrication process must be possible on the advanced process nodes used in microprocessors, currently in 5 or 7nm.
1.  The current required to switch states must be low, about ½ what is presently possible.