- 2019 [FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads](https://www.groundai.com/project/fuse-fusing-stt-mram-into-gpus-to-alleviate-off-chip-memory-access-overheads/1)

- 2018 [iCELIA: A Full-Stack Framework for STT-MRAM-Based Deep Learning Acceleration](http://alchem.usc.edu/portal/static/download/icella.pdf)



- 2019 digital-based memory [RAPIDNN: In-Memory Deep Neural Network Acceleration Framework](https://arxiv.org/pdf/1806.05794.pdf)

- year? [Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks](https://www.rle.mit.edu/eems/wp-content/uploads/2016/04/eyeriss_isca_2016.pdf) Yu-Hsin Chen,Joel Emer and Vivienne Sze


extracts representative operands by clustering method

2016 [Accelerating Machine Learning with Non-Volatile Memory: exploring device and circuit tradeoffs](https://researcher.watson.ibm.com/researcher/files/us-gwburr/Almaden_neuromorphicNVM_ICRC2016.pdf)

- [ISAAC: A Convolutional Neural Network Accelerator with In-Situ **Analog Arithmetic in Crossbars**](https://www.cs.utah.edu/~rajeev/pubs/isca16.pdf)


2016 video [ISAAC: An Analog Convolutional Neural Network Accelerator (Part II)](https://www.youtube.com/watch?v=0lPaKLzTKaU)